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Issues list

iotesters.Driver has deprecated in Chisel 3.5.3, should this tutorial changed to ChiselStage?
#172 opened Sep 10, 2022 by gerayking
"chisel-iotesters" -> "1.4.1+" in build.sbt breaks Vec code (which is also in your solutions)
#171 opened Mar 30, 2022 by FrancescoTerrosi
Is there any method to prevent the generation of lot of directory when using chisel PeekPokeTester?
#170 opened Jan 11, 2022 by ken881015
make -jN run Error and cannot locate project 'chisel' in 'chisel3' directory
#167 opened Nov 20, 2020 by irays18
I hope to study chisel but i can't start. please help me.
#165 opened Jun 7, 2020 by dldldlfma
2
Risc example broken with treadle backend bug
#159 opened May 4, 2020 by chick 3.2.0
@chick
xorR is broken in chisel-tutorial
#152 opened Nov 7, 2019 by adoerflinger
why the code of VendingMachineSwitch.scala in the tutorial generate if-else statement instead of case statement
#151 opened Sep 16, 2019 by qgzln
2
how to run chisel-tutorial in the IntelliJ IDE with Scala and SBT plug-ins?
#149 opened Jun 16, 2019 by Ravenwater
4
how to read a text file whose contents represents an array in testcase
#147 opened Apr 15, 2019 by botaichang
Need a consistent naming convention on variables
#146 opened Mar 25, 2019 by iBug
1
firrtl.passes.CheckInitialization$RefNotInitializedException
#145 opened Feb 22, 2019 by botaichang
can I generate verilog without sbt ?
#143 opened Feb 4, 2019 by balanx
12
question about Firrtl(IR) optimization
#142 opened Dec 22, 2018 by YingkunZhou
11
Error on generating Verilog
#141 opened Nov 11, 2018 by beatsnbytes
2
erorr running ./run-examples.sh GCD --backend-name verilator
#134 opened Aug 1, 2018 by eahmedsalman
error with sbt run
#133 opened Jul 31, 2018 by eahmedsalman
6
Conditional Assignments and Memories tutorial issue
#120 opened Mar 28, 2018 by barabanshek
2
AdderTest.scala get a wrong testing
#117 opened Mar 20, 2018 by citrus-lemon
1
Facing issue while generating verilog
#111 opened Dec 17, 2017 by Sairam-Ganti
7
synchronous memory description
#107 opened Nov 21, 2017 by schoeberl
Generated VCD
#83 opened Apr 27, 2017 by davidwende
3
sbt problem
#81 opened Mar 27, 2017 by ghost
10
Code in Wiki is dated
#80 opened Mar 7, 2017 by jackkoenig
3
discrepancy between Verilog and firrtl simulation
#66 opened Jan 20, 2017 by sols1
2
ProTip! no:milestone will show everything without a milestone.