Refactor the Next SSG transform to handle the inverse operation

[alexkirsz]

The original transform

The original behavior of the Next SSG transform is to remove getServerSideProps, getStaticProps, and getStaticPaths from Next.js page files so they can be bundled for the client. This is what enables the following code to work properly without advanced tree shaking:

import db from "db";
import PostCounter from 

export default function Home(props) {
  return <>{props.posts.length} post(s)</>;
}

const postsPromise = db.getPosts();

export async function getStaticProps() {
  return {
    props: {
      posts: await postsPromise,
    },
  };
}

The transform is able to remove both getStaticProps and all its exclusive, transitive dependencies, so this is what the client would see:

import PostCounter from "components/PostCounter";
export var __N_SSG = true;
export default function Home(props) {
    return __jsx(PostCounter, {
        count: props.posts.length
    });
}

Adding the inverse operation

However, to support proper HMR for these data exports, we need to be able to execute somewhat of an inverse operation: remove the default component export, but preserve all the rest. This allows Turbopack to bundle server-side only declarations, only re-rendering when one of these changes, instead of re-rendering on any server-side and client-side change.

From our module above, the updated transform is now also able to generate the following:

import db from "db";
const postsPromise = db.getPosts();
export async function getStaticProps() {
    return {
        props: {
            posts: await postsPromise
        }
    };
}

As you can see, this module is no longer importing the PostCounter, which means re-rendering will not invalidate when that counter changes. However, if the "db" module changes, we will still be able to detect a change and re-render.

Other notes

• I renamed the transform from "next_ssg" to "next_transform_strip_page_exports". It's much more verbose, but hopefully also much clearer about what it does at a glance.
• I took the liberty to clean up and comment some parts of the transform to make it more easily understandable (at least for someone like me, who hasn't written a lot of SWC code). I also fixed a few bugs and edge cases.
• I brought over the tests from the transform in the Next.js and added a couple of them.
• For now, only the StripDataExports filter is used. A future PR will build on this and @ForsakenHarmony's add json route for page data requests #2949 PR to actually implement SSR/SSG HMR.

Reviewing guide

1. The crux of the change is the move (and refactor) of the next ssg transform from https://github.com/vercel/turbo/pull/2968/files#diff-133d73657647ed793ca4782a73552650b32ad565094b1e0faf452ad58705499b to https://github.com/vercel/turbo/pull/2968/files#diff-d6442fa6af9b66e581f062739dd6de2419f5e8f6f3d97cfa63518c72b0a9ee3e.
2. I also added the errors.rs and fixture.rs tests. I adapted fixture.rs to execute on the two transform filters: data exports and default export.
3. Most of the tests in tests/ are copied from https://github.com/vercel/next.js/tree/canary/packages/next-swc/crates/core/tests. The changes I made are:
   i. https://github.com/vercel/turbo/pull/2968/files#diff-774abee6a1bf139c9ce55e226bf15b52e56ea091170ee5d6295c191fd8d793c7: made this one symmetric for both strip data and strip default transforms.
   ii. https://github.com/vercel/turbo/pull/2968/files#diff-4792266a264dc67da93748d2c6522917f860527a689891bd5f8f4add9841e7f6 wasn't supported before AFAIK.
   iii. https://github.com/vercel/turbo/pull/2968/files#diff-a3b12adbce1dec40f39ff8af13ffecbe7f6963e21bc402cef6332ecf5018877e similar to i.

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[github-actions]

Benchmark for f933c7d

Test	Base	PR	%	Significant %
bench_startup/Turbopack RSC/1000 modules	2255.68ms ± 17.51ms	2129.12ms ± 6.89ms	-5.61%	-3.50%

Click to view full benchmark

Test	Base	PR	%	Significant %
bench_hmr_to_commit/Turbopack CSR/1000 modules	7791.93µs ± 62.03µs	7783.42µs ± 60.28µs	-0.11%
bench_hmr_to_commit/Turbopack RCC/1000 modules	8053.79µs ± 59.00µs	8077.03µs ± 65.84µs	+0.29%
bench_hmr_to_commit/Turbopack RSC/1000 modules	845.48ms ± 19.51ms	836.91ms ± 27.06ms	-1.01%
bench_hmr_to_commit/Turbopack SSR/1000 modules	7845.82µs ± 47.66µs	7904.08µs ± 60.19µs	+0.74%
bench_hmr_to_eval/Turbopack CSR/1000 modules	6860.93µs ± 53.91µs	6887.66µs ± 65.07µs	+0.39%
bench_hmr_to_eval/Turbopack RCC/1000 modules	6949.01µs ± 48.00µs	6998.34µs ± 64.75µs	+0.71%
bench_hmr_to_eval/Turbopack SSR/1000 modules	6910.31µs ± 52.67µs	6933.88µs ± 60.62µs	+0.34%
bench_hydration/Turbopack RCC/1000 modules	3369.39ms ± 25.32ms	3410.23ms ± 10.78ms	+1.21%
bench_hydration/Turbopack RSC/1000 modules	2548.75ms ± 28.35ms	2574.66ms ± 43.71ms	+1.02%
bench_hydration/Turbopack SSR/1000 modules	2923.03ms ± 10.82ms	2913.38ms ± 11.90ms	-0.33%
bench_startup/Turbopack CSR/1000 modules	1419.51ms ± 3.59ms	1412.93ms ± 5.74ms	-0.46%
bench_startup/Turbopack RCC/1000 modules	2617.49ms ± 17.26ms	2642.99ms ± 8.81ms	+0.97%
bench_startup/Turbopack RSC/1000 modules	2255.68ms ± 17.51ms	2129.12ms ± 6.89ms	-5.61%	-3.50%
bench_startup/Turbopack SSR/1000 modules	2288.75ms ± 8.74ms	2300.09ms ± 7.03ms	+0.50%

[kdy1]

I'm not sure, just worried.

[github-actions]

Benchmark for cdf405d

Click to view benchmark

Test	Base	PR	%	Significant %
bench_hmr_to_commit/Turbopack CSR/1000 modules	8568.76µs ± 63.92µs	8623.98µs ± 57.05µs	+0.64%
bench_hmr_to_commit/Turbopack RCC/1000 modules	8897.77µs ± 80.90µs	8938.84µs ± 94.02µs	+0.46%
bench_hmr_to_commit/Turbopack RSC/1000 modules	853.51ms ± 14.82ms	842.93ms ± 15.02ms	-1.24%
bench_hmr_to_commit/Turbopack SSR/1000 modules	8680.29µs ± 54.82µs	8641.82µs ± 68.59µs	-0.44%
bench_hmr_to_eval/Turbopack CSR/1000 modules	7675.19µs ± 48.37µs	7557.47µs ± 100.60µs	-1.53%
bench_hmr_to_eval/Turbopack RCC/1000 modules	7715.25µs ± 91.42µs	7763.76µs ± 58.41µs	+0.63%
bench_hmr_to_eval/Turbopack SSR/1000 modules	7707.51µs ± 62.70µs	7708.08µs ± 53.37µs	+0.01%
bench_hydration/Turbopack RCC/1000 modules	3601.51ms ± 12.43ms	3517.75ms ± 41.67ms	-2.33%
bench_hydration/Turbopack RSC/1000 modules	2751.02ms ± 43.11ms	2783.71ms ± 47.48ms	+1.19%
bench_hydration/Turbopack SSR/1000 modules	3059.16ms ± 6.95ms	3050.02ms ± 14.74ms	-0.30%
bench_startup/Turbopack CSR/1000 modules	1472.24ms ± 4.98ms	1462.16ms ± 5.24ms	-0.69%
bench_startup/Turbopack RCC/1000 modules	2750.76ms ± 9.46ms	2642.25ms ± 50.55ms	-3.94%
bench_startup/Turbopack RSC/1000 modules	2262.40ms ± 29.94ms	2334.18ms ± 40.32ms	+3.17%
bench_startup/Turbopack SSR/1000 modules	2382.66ms ± 8.02ms	2379.05ms ± 6.77ms	-0.15%

[kdy1]

I think the logic is good, but I forgot to reset the flag frequently while working on swc, and the mistake caused many issues.

[github-actions]

Benchmark for 1f01840

Click to view benchmark

Test	Base	PR	%	Significant %
bench_hmr_to_commit/Turbopack CSR/1000 modules	8141.71µs ± 76.08µs	8061.26µs ± 44.01µs	-0.99%
bench_hmr_to_commit/Turbopack RCC/1000 modules	8305.90µs ± 58.26µs	8291.65µs ± 89.73µs	-0.17%
bench_hmr_to_commit/Turbopack RSC/1000 modules	460.70ms ± 1.74ms	470.02ms ± 4.27ms	+2.02%
bench_hmr_to_commit/Turbopack SSR/1000 modules	8122.12µs ± 44.76µs	8187.12µs ± 49.11µs	+0.80%
bench_hmr_to_eval/Turbopack CSR/1000 modules	7100.99µs ± 47.10µs	7078.41µs ± 71.24µs	-0.32%
bench_hmr_to_eval/Turbopack RCC/1000 modules	7280.77µs ± 39.04µs	7312.19µs ± 50.28µs	+0.43%
bench_hmr_to_eval/Turbopack SSR/1000 modules	7132.27µs ± 55.12µs	7277.83µs ± 54.25µs	+2.04%
bench_hydration/Turbopack RCC/1000 modules	3272.41ms ± 7.80ms	3285.18ms ± 12.78ms	+0.39%
bench_hydration/Turbopack RSC/1000 modules	2763.50ms ± 6.49ms	2787.30ms ± 9.18ms	+0.86%
bench_hydration/Turbopack SSR/1000 modules	2594.04ms ± 9.23ms	2572.96ms ± 11.91ms	-0.81%
bench_startup/Turbopack CSR/1000 modules	1601.70ms ± 6.27ms	1598.90ms ± 4.32ms	-0.17%
bench_startup/Turbopack RCC/1000 modules	2450.73ms ± 9.41ms	2458.86ms ± 9.73ms	+0.33%
bench_startup/Turbopack RSC/1000 modules	2339.63ms ± 6.07ms	2340.31ms ± 9.85ms	+0.03%
bench_startup/Turbopack SSR/1000 modules	1999.82ms ± 6.71ms	2005.43ms ± 4.21ms	+0.28%

[github-actions]

Benchmark for cd8cee4

Test	Base	PR	%	Significant %
bench_startup/Turbopack RSC/1000 modules	2363.06ms ± 6.40ms	2424.01ms ± 15.75ms	+2.58%	+0.70%

Click to view full benchmark

Test	Base	PR	%	Significant %
bench_hmr_to_commit/Turbopack CSR/1000 modules	7885.21µs ± 42.90µs	7921.85µs ± 51.09µs	+0.46%
bench_hmr_to_commit/Turbopack RCC/1000 modules	8182.30µs ± 51.23µs	8187.46µs ± 46.56µs	+0.06%
bench_hmr_to_commit/Turbopack RSC/1000 modules	478.47ms ± 2.28ms	479.56ms ± 2.65ms	+0.23%
bench_hmr_to_commit/Turbopack SSR/1000 modules	7949.21µs ± 53.67µs	8023.32µs ± 29.05µs	+0.93%
bench_hmr_to_eval/Turbopack CSR/1000 modules	7051.43µs ± 54.05µs	7021.03µs ± 48.21µs	-0.43%
bench_hmr_to_eval/Turbopack RCC/1000 modules	7159.78µs ± 50.33µs	7185.94µs ± 60.80µs	+0.37%
bench_hmr_to_eval/Turbopack SSR/1000 modules	7145.79µs ± 86.26µs	7076.51µs ± 85.21µs	-0.97%
bench_hydration/Turbopack RCC/1000 modules	3297.53ms ± 9.32ms	3337.44ms ± 17.05ms	+1.21%
bench_hydration/Turbopack RSC/1000 modules	2792.07ms ± 9.65ms	2794.73ms ± 8.79ms	+0.10%
bench_hydration/Turbopack SSR/1000 modules	2594.93ms ± 14.30ms	2608.55ms ± 9.66ms	+0.52%
bench_startup/Turbopack CSR/1000 modules	1620.77ms ± 4.46ms	1620.55ms ± 5.23ms	-0.01%
bench_startup/Turbopack RCC/1000 modules	2484.12ms ± 9.74ms	2487.52ms ± 7.54ms	+0.14%
bench_startup/Turbopack RSC/1000 modules	2363.06ms ± 6.40ms	2424.01ms ± 15.75ms	+2.58%	+0.70%
bench_startup/Turbopack SSR/1000 modules	2024.72ms ± 3.98ms	2026.17ms ± 5.79ms	+0.07%