Last-Level-Cache-Simulator

CURRENT STATUS : stable

Basic features

A generic trace driven cache simulator of last level Cache for a new processor that can be used with up to three other processors in a shared memory configuration.
It employs a write allocate policy and uses the MESI protocol to ensure coherence.
The replacement policy is implemented with a true-LRU scheme.
The simulator was configurable in terms of cache size, block size and associativity.

Download all the project files into your local system.

Mentor Questasim\Modelsim

Step by step instructions to setup the project in your local machine

Open the directory in your local machine which contains all files of the project
Open terminal with the same directory

Execute make command in the command line which will execute all_traces.txt trace file
For executing other trace files use - make trace_name=<Trace file name>

This project has been developed with Mentor Questasim.

This project is licensed under the open-source license

Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
L3Cache_Documentation.pdf		L3Cache_Documentation.pdf
Makefile		Makefile
README.md		README.md
Trace_handler.sv		Trace_handler.sv
all_traces.txt		all_traces.txt
cache.sv		cache.sv
cache_controller.sv		cache_controller.sv
cache_pkg.sv		cache_pkg.sv
cache_set_fill_hits_misses.txt		cache_set_fill_hits_misses.txt
cpu_read.txt		cpu_read.txt
cpu_write.txt		cpu_write.txt
snoop_Invalidate.txt		snoop_Invalidate.txt
snoop_read.txt		snoop_read.txt
snoop_rwim.txt		snoop_rwim.txt
snoop_write.txt		snoop_write.txt