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enabled_when_ready (in .bs)? #605

Closed Answered by quark17
rossc719g asked this question in Q&A
Aug 22, 2023 · 1 comments · 2 replies
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The feature is not documented and not really tested, so in that respect it doesn't exist.

The BSV parser does accept it and BSC does do something when it sees that attribute, but it's probably not the right behavior or the full behavior. So some work would be needed.

The one file in the test suite that has this attribute is bsc.bluesim/to_systemc/getput/GetPutTest.bsv, so you can compile that and see what the behavior is. I believe that what BSC does is, when generating a module that has an enabled_when_ready attribute, to generate Verilog that uses the RDY signal anywhere it would normally use the EN signal, and to still generate the EN port, but it is unused; there is no check that subm…

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