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Verilog attributes? #619

Answered by quark17
nkyparissas asked this question in Q&A
Sep 28, 2023 · 1 comments · 1 reply
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Issue #445 is an enhancement request to support this. In the meantime, a workaround is to use the doc attribute combined with a post-processing script.

The doc attribute can be used to put comments in the generated Verilog. You can apply it to a module, like this:

(* doc = "ATTRIBUTE: keep_hierarchy = \"yes\"" *)
(* synthesize *)
module mkTest (Ifc);

Then you can tell BSC to run a post-processing script on its generated modules, using the flag -verilog-filter:

bsc  -verilog  -verilog-filter doc_to_attr.py  Test.bsv

Then you'd need to write a script (doc_to_attr.py say), which looks for something unique in the comments (such as ATTRIBUTE:) and adjusts that into an attribute. Unfortunatel…

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