Skip to content

Issues: chipsalliance/verible

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Author
Filter by author
Label
Filter by label
Use alt + click/return to exclude labels
or + click/return for logical OR
Projects
Filter by project
Milestones
Filter by milestone
Assignee
Filter by who’s assigned
Sort

Issues list

Feature Request: do not add spaces around logical keywords formatter Verilog code formatter issues
#2179 opened May 7, 2024 by ewolff96
verible.filelist empty file exception language-server Language server related issues
#2178 opened May 7, 2024 by sconwayaus
VSCode - Generate and maintain verible.filelist language-server Language server related issues
#2177 opened May 7, 2024 by sconwayaus
linter cannot find macro defined in a different file style-linter Verilog style-linter issues
#2173 opened May 4, 2024 by samimia-swks
automatically comment preprocessor conditionals enhancement New feature or request good first issue Good for newcomers preprocessor anything related to preprocessing (conditionals, macros, etc.) style-linter Verilog style-linter issues
#2171 opened Apr 30, 2024 by fangism
Parser rejects streaming operators that use the "with" clause rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2167 opened Apr 19, 2024 by fpgauserdude
nix package for mac not available
#2163 opened Apr 16, 2024 by thuvasooriya
[unpacked-dimensions-range-ordering] - configuration enhancement New feature or request style-linter Verilog style-linter issues
#2161 opened Apr 16, 2024 by sconwayaus
verible-verilog-obfuscate crashes when program has pragma directive rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2159 opened Apr 15, 2024 by rafasumi
Return type using type(...) throws syntax error rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2157 opened Apr 12, 2024 by goekce
Long localparam lines are not formatted formatter Verilog code formatter issues
#2156 opened Apr 12, 2024 by goekce
verible-verilog-syntax does not fully support `protect directive rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2153 opened Apr 3, 2024 by craigc40
verible-verilog-syntax does not support dimensioned parameter in list of parameter assignments rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2152 opened Apr 2, 2024 by craigc40
There is no syntax highlighting in VS Code language-server Language server related issues
#2149 opened Mar 23, 2024 by DeflateAwning
Struct signals not checked for signal-name-style style-linter Verilog style-linter issues
#2147 opened Mar 21, 2024 by matlupi
Unexpected formatting of interface classes formatter Verilog code formatter issues
#2145 opened Mar 14, 2024 by sriyerg
The formatter combines the compiler directives into one line of code formatter Verilog code formatter issues
#2131 opened Mar 6, 2024 by EhsanJokar1
How to debug VSCode LS? language-server Language server related issues
#2127 opened Mar 3, 2024 by shareefj
typedef array of interfaces not supported rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2114 opened Feb 20, 2024 by matlupi
Property definition with disable iff before event fails rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2108 opened Feb 15, 2024 by matlupi
ProTip! Updated in the last three days: updated:>2024-05-08.