Property definition with disable iff before event fails

[matlupi]

Describe the bug

The syntax checker rejects properties with the disable iff defined before the sampling event in a property.

To Reproduce

test.sv

module test;
  logic clk;
  logic rst;
  logic a;
  logic b;

  // accepted
  property tp;
    @(posedge clk) disable iff (rst) a |-> b;
  endproperty
  assert property (tp);

  // rejected
  property tpr;
    disable iff (rst) @(posedge clk) a |-> b;
  endproperty
  assert property (tpr);

  assert property (@(posedge clk) disable iff (rst) a|->b); // accepted
  assert property (disable iff (rst) @(posedge clk) a|->b); // rejected
endmodule

verible-verilog-lint test.sv

Actual behavior:

Rejects valid code

$ verible-verilog-lint test.sv 
test.sv:15:23: syntax error at token "@"
test.sv:16:3-13: syntax error at token "endproperty"
test.sv:20:38: syntax error at token "@"

Expected behavior

All options above are valid and should be accepted.