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Describe the bug
Valid syntax is rejected
To Reproduce
Run
verible-verilog-syntax test.sv
test.sv as follows
test.sv
interface t_interface; endinterface package test; typedef virtual t_interface t_vif_array []; endpackage
Version used
% verible-verilog-syntax --version v0.0-3389-ga1cd07b1 Commit 2023-07-26 Built 2023-07-26T21:32:29Z
Actual behavior:
Code rejected
test.sv:5:43: syntax error at token "["
Expected behavior
Accepted syntax.
The text was updated successfully, but these errors were encountered:
No branches or pull requests
Describe the bug
Valid syntax is rejected
To Reproduce
Run
test.sv
as followsVersion used
Actual behavior:
Code rejected
Expected behavior
Accepted syntax.
The text was updated successfully, but these errors were encountered: