[Feature request] Signal names in the module instantiation (align brackets and add spaces inside)

[alexeykosinov]

Test case

    zynq zynq_inst (
        .o_axi_clk (zynq_axi_aclk),
        .o_axi_rstn (zynq_axi_aresetn),
        .o_gpio (zynq_o_gpio),
        .i_gpio (zynq_i_gpio),
        .i_pl_ps_irq (16'd0) 
    );

Actual output

    zynq zynq_inst (
        .o_axi_clk     (zynq_axi_aclk),
        .o_axi_rstn    (zynq_axi_aresetn),
        .o_gpio        (zynq_o_gpio),
        .i_gpio        (zynq_i_gpio),
        .i_pl_ps_irq   (16'd0)
    );

Expected or suggested output

    zynq zynq_inst (
        .o_axi_clk      ( zynq_axi_aclk     ),
        .o_axi_rstn     ( zynq_axi_aresetn  ),
        .o_gpio         ( zynq_o_gpio       ),
        .i_gpio         ( zynq_i_gpio       ),
        .i_pl_ps_irq    ( 16'd0             ) 
    );

I think this will improve the code readability.
So it will be cool if you add this option in the future releases!

Thanks!