The formatter combines the compiler directives into one line of code

[EhsanJokar1]

The formatter combines these directives into one line.

Test case

 `resetall
 `timescale 1ns / 1ps
 `default_nettype none

Actual output

 `resetall `timescale 1ns / 1ps `default_nettype none

Is this the expected behavior?
If not, how can we prevent this combination.
One solution is using // verilog_format: off and // verilog_format: on. But, is there any way to fix this?