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verible-verilog-syntax does not fully support `protect directive #2153

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craigc40 opened this issue Apr 3, 2024 · 0 comments
Open

verible-verilog-syntax does not fully support `protect directive #2153

craigc40 opened this issue Apr 3, 2024 · 0 comments
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rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).

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@craigc40
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craigc40 commented Apr 3, 2024

Describe the bug

Valid syntax rejected. Verible-verilog-syntax does not allow 'protect in the following cases:

  • anywhere within a primitive definition
  • between module name and port list

Version

% verible-verilog-syntax --version
    v0.0-3471-g9cb45092
    Commit	2023-12-23
    Built	2023-12-23T08:07:18Z 

To Reproduce

The following code all fails verible-verilog-syntax with syntax errors:

// protect keyword between primitive name and port list
primitive mux_p1
`protect
    (out, sel, a, b);
    output  out;
    input   sel, a, b;

    table
    // sel  a   b       out
        0   1   ?   :   1;
        0   0   ?   :   0;
        1   ?   0   :   0;
        1   ?   1   :   1;
        x   0   0   :   0;
        x   1   1   :   1;
    endtable
`endprotect
endprimitive
// protect keyword after primitive port list
primitive mux_p2 (out, sel, a, b);
`protect
    
    output  out;
    input   sel, a, b;

    table
    // sel  a   b       out
        0   1   ?   :   1;
        0   0   ?   :   0;
        1   ?   0   :   0;
        1   ?   1   :   1;
        x   0   0   :   0;
        x   1   1   :   1;
    endtable
`endprotect
endprimitive
// protect keyword between module name and port list
module mux_m 
`protect
(out, sel, a, b);
    output  out;
    input   sel, a, b;

    assign out = sel? a : b;
`endprotect
endmodule

Run

verible-verilog-syntax testme.sv with any of the above

Actual behavior:

Code rejected - error messages shown here are for the first case above:

testme.sv:4:1-8: syntax error at token "`protect"
testme.sv:6:3-8: syntax error at token "output"
testme.sv:7:3-7: syntax error at token "input"
testme.sv:9:3-7: syntax error at token "table"
testme.sv:12:7: syntax error at token "0"
testme.sv:13:7: syntax error at token "1"
testme.sv:14:7: syntax error at token "1"
testme.sv:15:7: syntax error at token "x"
testme.sv:16:7: syntax error at token "x"
testme.sv:17:3-10: syntax error at token "endtable"

Expected behavior

Accepts syntax

@craigc40 craigc40 added the rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017). label Apr 3, 2024
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