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Feature Request: do not add spaces around logical keywords #2179

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ewolff96 opened this issue May 7, 2024 · 0 comments
Open

Feature Request: do not add spaces around logical keywords #2179

ewolff96 opened this issue May 7, 2024 · 0 comments
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formatter Verilog code formatter issues

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@ewolff96
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ewolff96 commented May 7, 2024

Currently the formatter forces spaces around logical test keywords such as if, wait, assert, while, etc. It would be helpful if there was an option to do the opposite of this and instead remove all whitespace between the keyword and parentheses. This would make the formatter more usable for codebases that avoid whitespace usage around these keywords similar to the whitespace and parentheses usage for functions.

Input

if     (variable) begin
  wait(done);
  assert(complete);
  myFunction(i,j,k);
end

while (i < k);

Actual output

if (variable) begin
  wait (done);
  assert (complete);
  myFunction(i, j, k);
end

while (i < k);

Expected or suggested output

if(variable) begin
  wait(done);
  assert(complete);
  myFunction(i,j,k);
end

while(i < k);
@ewolff96 ewolff96 added the formatter Verilog code formatter issues label May 7, 2024
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Labels
formatter Verilog code formatter issues
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