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Università di Bologna
- Bologna, Italy
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arty-s7-examples
arty-s7-examples PublicExamples to practice with FPGA design on the Digilent Arty-S7 development board.
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HiFive-Power-Monitor
HiFive-Power-Monitor PublicLabVIEW and Python tools to monitor the power consumption of SiFive HiFive boards.
LabVIEW
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common_cells
common_cells PublicForked from pulp-platform/common_cells
Common SystemVerilog components
SystemVerilog
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coding-challenges-booklet
coding-challenges-booklet PublicSolutions to the exercises in the Coding Challenge Booklet, implemented in Rust.
Rust
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