VeeR EL2 Core
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Updated
Jun 7, 2024 - SystemVerilog
VeeR EL2 Core
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Common SystemVerilog RTL modules for RgGen
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
RISCV CPU implementation in SystemVerilog
RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
Performance counter to measure latency between two AXI Stream interfaces with pattern matching as trigger.
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
VeeR EH1 core
Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022
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