MNT Bench - An MNT tool for Benchmarking FCN circuits
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Updated
Jun 7, 2024 - HTML
MNT Bench - An MNT tool for Benchmarking FCN circuits
Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
This repository serves as an archive of all the knowledge I acquired and encountered during the VSD-Advanced Physical Design workshop. I have utilised several snippets to demonstrate the ideas I gathered in the lectures and the outcomes of my lab module.
SerDes RTL design, verification using UVM and Physical design.
This repository is my entry into scripting using TCL and an attempt to understand it's nuances in physical design flow in VLSI
VSDMemSOC Implementation flow:: RTL2GDSII
GitHub repository dedicated to VLSI ASIC Design using open-source tools! A simple Vedic Multiplier is Forged, through the entire RTL to GDS process that meets various PPA
RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
Design, layout, and simulation files of the paper "Atomic Defect-Aware Physical Design of Silicon Dangling Bond Logic on the H-Si(100)-2×1 Surface" by M. Walter, J. Croshaw, S. S. H. Ng, K. Walus, R. Wolkow, and R. Wille in DATE 2024.
EDA physical synthesis optimization kit
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
generic NetList data structure for VLSI
Final project at San Jose State University
PrUcess is a low-power multi-clock configurable digital processing system that executes commands (unsigned arithmetic operations, logical operations, register file read & write operations) which are received from an external source through UART receiver module and it transmits the commands' results through the UART transmitter module.
CUGR, VLSI Global Routing Tool Developed by CUHK
Creating this repo to document the learnings from the workshop Advanced Physical Design using OpenLANE/SKY130 conducted by VSD
Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.
This repository contains all the information included in the beginner SoC/physical design using open-source EDA tools organized by VLSI System Design Corporation. This workshop helped me gain hands-on experience with tools that are used in the physical design flow.
Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian
Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.
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