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Variable shadowing rule (Rebase of #790) #2133
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Codecov ReportAll modified and coverable lines are covered by tests ✅
❗ Your organization needs to install the Codecov GitHub app to enable full functionality. Additional details and impacted files@@ Coverage Diff @@
## master #2133 +/- ##
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+ Coverage 92.92% 92.94% +0.01%
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Files 359 360 +1
Lines 26673 26746 +73
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+ Hits 24787 24860 +73
Misses 1886 1886 ☔ View full report in Codecov by Sentry. |
namespace verilog { | ||
namespace analysis { | ||
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class InstanceShadowRule : public verible::SyntaxTreeLintRule { |
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Can you add a full description with a few examples to the class docstring?
"bit out;\n", | ||
"endfunction\n"}, | ||
}; | ||
RunLintTestCases<VerilogAnalyzer, InstanceShadowRule>( |
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What should happen with test cases that resemble K&R style declarations, like:
module foo(a, b);
input wire a; // not a shadow, but attaches a type to the `a` port
output reg b; // not a shadow
endmodule
Can you include a few cases like this?
This is a rebase of #790 to compile with head.
Fixing #247