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Variable shadowing rule (Rebase of #790) #2133

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@hzeller hzeller commented Mar 7, 2024

This is a rebase of #790 to compile with head.

Fixing #247

@hzeller hzeller force-pushed the feature-20240306-rebase-790 branch from 6ffb916 to 0977914 Compare March 7, 2024 03:44
@hzeller hzeller mentioned this pull request Mar 7, 2024
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codecov-commenter commented Mar 7, 2024

Codecov Report

All modified and coverable lines are covered by tests ✅

Project coverage is 92.94%. Comparing base (46de0f6) to head (0977914).

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Additional details and impacted files
@@            Coverage Diff             @@
##           master    #2133      +/-   ##
==========================================
+ Coverage   92.92%   92.94%   +0.01%     
==========================================
  Files         359      360       +1     
  Lines       26673    26746      +73     
==========================================
+ Hits        24787    24860      +73     
  Misses       1886     1886              

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@hzeller hzeller requested a review from fangism March 7, 2024 18:28
namespace verilog {
namespace analysis {

class InstanceShadowRule : public verible::SyntaxTreeLintRule {
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Can you add a full description with a few examples to the class docstring?

"bit out;\n",
"endfunction\n"},
};
RunLintTestCases<VerilogAnalyzer, InstanceShadowRule>(
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What should happen with test cases that resemble K&R style declarations, like:

module foo(a, b);
input wire a;   // not a shadow, but attaches a type to the `a` port
output reg b;  // not a shadow
endmodule

Can you include a few cases like this?

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4 participants