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[v18.x] deps: V8: cherry-pick 5fe919f78321 #45587

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[v18.x] deps: V8: cherry-pick 5fe919f78321 #45587

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2 changes: 1 addition & 1 deletion common.gypi
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Expand Up @@ -36,7 +36,7 @@

# Reset this number to 0 on major V8 upgrades.
# Increment by one for each non-official patch applied to deps/v8.
'v8_embedder_string': '-node.21',
'v8_embedder_string': '-node.22',

##### V8 defaults for Node.js #####

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4 changes: 4 additions & 0 deletions deps/v8/src/wasm/baseline/ppc/liftoff-assembler-ppc.h
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Expand Up @@ -1455,6 +1455,7 @@ bool LiftoffAssembler::emit_type_conversion(WasmOpcode opcode,
fcmpu(src.fp(), kScratchDoubleReg);
bunordered(trap);

mtfsb0(VXCVI); // clear FPSCR:VXCVI bit
fctiwz(kScratchDoubleReg, src.fp());
MovDoubleLowToInt(dst.gp(), kScratchDoubleReg);
mcrfs(cr7, VXCVI);
Expand All @@ -1463,6 +1464,7 @@ bool LiftoffAssembler::emit_type_conversion(WasmOpcode opcode,
}
case kExprI32UConvertF64:
case kExprI32UConvertF32: {
mtfsb0(VXCVI); // clear FPSCR:VXCVI bit
ConvertDoubleToUnsignedInt64(src.fp(), r0, kScratchDoubleReg,
kRoundToZero);
mcrfs(cr7, VXCVI); // extract FPSCR field containing VXCVI into cr7
Expand All @@ -1478,6 +1480,7 @@ bool LiftoffAssembler::emit_type_conversion(WasmOpcode opcode,
fcmpu(src.fp(), kScratchDoubleReg);
bunordered(trap);

mtfsb0(VXCVI); // clear FPSCR:VXCVI bit
fctidz(kScratchDoubleReg, src.fp());
MovDoubleToInt64(dst.gp(), kScratchDoubleReg);
mcrfs(cr7, VXCVI);
Expand All @@ -1490,6 +1493,7 @@ bool LiftoffAssembler::emit_type_conversion(WasmOpcode opcode,
fcmpu(src.fp(), kScratchDoubleReg);
bunordered(trap);

mtfsb0(VXCVI); // clear FPSCR:VXCVI bit
fctiduz(kScratchDoubleReg, src.fp());
MovDoubleToInt64(dst.gp(), kScratchDoubleReg);
mcrfs(cr7, VXCVI);
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