VUnit is a unit testing framework for VHDL/SystemVerilog
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Updated
May 23, 2024 - VHDL
VUnit is a unit testing framework for VHDL/SystemVerilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…
HDL support for VS Code
This Repository invites freelancer friendly neighbourhood developers to contribute to open source .
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
Gigabit Ethernet UDP communication driver
High throughput JPEG decoder in Verilog for FPGA
Image Processing Toolbox in Verilog using Basys3 FPGA
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
This is a tutorial on standard digital design flow
中山大学计算机组成原理实验 (2018 秋):用 Verilog 设计并实现的简易单周期和多周期 CPU
A complete open-source design-for-testing (DFT) Solution
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
Interface Protocol in Verilog
A simple implementation of a UART modem in Verilog.
Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
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